AI-infrastructures for Failure Analysis
Reliability challenging in 3D IC packaging technology-Electromigration and thermomigration in solder joints
Multiscale imaging of nanoelectronics using X-rays
Chip-scale Packages: Failure Analysis Techniques, Challenges And Solutions
Defect-based testing for complementary field effect transistor technologies
Electron lens aberration correction technologies and TEM/STEM techniques
Characterization of nano-materials and biocompatible materials for semiconductor applications
Data-driven materials science paradigm approach in failure analysis
LED performance, reliability and failures
Reliability assessment for oxide based neuromorphic devices and systems
Surface analysis technique used in the microelectronics industry
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University of Klagenfurt, Austria
FA labs clearly acknowledge the advantages of employing AI methods to automate various routines. Recent FA conferences featured presentations and tutorials highlighting numerous AI applications, such as using convolutional networks to identify physical failures from images or waveforms, detecting probes for their accurate placement on samples, or optimizing advanced packaging processes. The growing number of AI components represents a significant challenge for the IT infrastructure of FA labs, which must not only guarantee consistent development operations of AI components but also their smooth integration into different tools used in FA workflows. This includes automatic suggestion of the right components for the performed analysis tasks, interoperability of their results, as well as retrieving know-how and information to help an engineer finish the job efficiently.
The keynote addresses the AI lifecycle within an FA lab, focusing on both data and software components. The data lifecycle is fundamental to all AI applications, which rely on consistent and sustainable methods for data extraction, annotation, and storage. Specifically, the talk highlights the importance of standardization to ensure interoperability among various systems, including AI components, databases, and monitoring and analytical tools. Finally, we provide an overview of implementation strategies for data infrastructures, drawing from practical experiments conducted in recent research projects. From the perspective of AI components, the keynote examines well-established approaches to their development and operational processes, discussing various implications for the FA environment. We illustrate these concepts through various AI applications, including physical failure detection in images, information retrieval using generative AI, and automatic planning for FA problem-solving with large language models.
Konstantin Schekotihin is an associate professor at AAUK. His research focus lies mainly on various aspects of hybrid AI systems that combine deep learning methods for computer vision and natural language processing with symbolic AI approaches based on knowledge representation and reasoning. Obtained research results were successfully applied to various industrial projects on failure analysis and diagnosis, cyber-physical systems, configuration, planning, scheduling, and recommendation. He is the author of more than 90 papers in these fields that were published in top AI conferences and journals and were distinguished with six best paper awards. In the area of semiconductor failure analysis, Konstantin is actively publishing in prestigious venues, including IEEE IPFA, ISTFA, and the EDFAS Journal. His papers cover different AI approaches to automation of failure analysis routines, such as standardization using ontologies, image-based failure detection with convolutional neural networks, information retrieval with large language models, and development of AI infrastructures for failure analysis laboratories.
Professor Fan-Yi Ouyang received her B.Sc and M.S. degree in Engineering and System Science from National Tsing Hua University at Hsinchu, Taiwan and Ph.D. in Material Science and Engineering, from University of California, Los Angeles in USA. She worked at Intel Corporation, Portland Technology Development Center as Quality and Reliability Engineer from 2007 to 2010. She then joined the Department of Engineering and System Science at National Tsing Hua University in Hsinchu in 2010 and is currently a Professor in the Department of Engineering and System Science and joint Professor in the College of Semiconductor Research. She is also Associate Director in the Center for Nanotechnology, Materials Science, and Microsystems at National Tsing Hua University in Taiwan. Dr. Ouyang achieves Senior HEA fellowship (SFEA) of the Higher Education Academy (HEA). She is a recipient of Young Leader Professional Development Award for functional material division of The Minerals, Metals and Materials Society. She also received the Young Scholar Award of The Materials Research Society-Taiwan in 2020, Excellent Young Professional Award of Taiwan Association for Coating and Thin Film Technology in 2020, and Excellent Young Professional Award of Taiwan Vacuum Association in 2023, respectively. Her current research interests include thin film material science, reliability science in microelectronic devices, and Low-temperature bonding processes in advanced electronic packaging technology.
With the development of the microelectronic industry, three-dimensional integration technology has been regarded as a prominent method to achieve the smaller featured size and higher performance for the consumer electronic market. The application environment becomes harsher for high power or high switching frequency applications such as electric vehicles or 5G communications. As the scaling of solder-based micropumps and harsher application environment, many new reliability issues have emerged for solder-based interconnection. This talk will focus on the reliability issues of electromigration and thermomigration in small-scale solder joints for advanced packing technology. Firstly, I will talk about the issues of solder joint technology when the size/pitch of the bumps continues to scale down. Then, I will introduce the failure mechanism of solder joints under current stressing, high Joule heating, and temperature gradient. Next, I will discuss how to improve the electromigration and thermomigration resistance of Pb-free solder joints in detail.
Head of the Center for Photon Science
Paul Scherrer Institut, Villigen PSI, Switzerland
Gabriel Aeppli is Professor of Physics at the ETH Zurich and the EPF Lausanne. He is also head of the Center for Photon Science at the Paul Scherrer Institute. His current research focuses on the implications of photon science for data technology and healthcare. He received a doctorate in electrical engineering at the Massachusetts Institute of Technology (MIT), Cambridge, USA, and spent most of his career in the private sector (NEC, Bell Laboratories, and IBM), where he worked on a variety of subjects such as liquid crystals and magnetic data storage. He then cofounded and became director of the London Centre for Nanotechnology, Quain Professor at University College London, and also co-founded the Bio-Nano Consulting company. He is a consultant for many private and public organizations worldwide (in China, Australia, Europe, and the USA) which deal with financing, evaluating, and managing technology. He is an elected member of the American Academy of Arts and Sciences, the US National Academy of Sciences, and the Royal Society (London) and has received many other awards, including the Mott Prize of the Institute of Physics in London and the Oliver Buckley Prize of the American Physical Society. Gabriel Aeppli has been a member of the Swiss Science Council since 2016.
G. Aeppli
Department of Physics and Quantum Center, ETHZ, CH-8093, Zürich, Switzerland
Institut de Physique, EPFL, CH-1015 Lausanne, Switzerland
Paul Scherrer Institut, CH-5232, Villigen, Switzerland
It is remarkable that semiconductor technology is more advanced in its capacity to create complex systems than in the ability to image the outcomes. Here we describe X-ray techniques to image, with minimal destruction, semiconductor heterostructures, devices, and systems. In particular, ptychography, a mixed real-space/reciprocal-space (“wavelet”) technique, provides three-dimensional images of integrated circuits at steadily improving resolution, now at four nanometers with the application of “burst” data collection. In addition, fluorescence can be used for chemical mapping, while soft X-ray photoemission accesses directly the electrons responsible for device functionality, as well as providing details on confining potentials. The future prospects for X-ray diagnostics of nanoelectronics are very strong given worldwide investment in next-generation synchrotrons and free-electron lasers.
Marvell Technology, Technical Director of Failure Analysis
Susan Li is a Technical Director of Failure Analysis at Marvell Technology. She is currently working with internal teams and outside service labs to develop tools and techniques for supporting failures analysis on IC devices using leading edge technology nodes and advanced 2.5D and 3D packaging.
During her long tenure with AMD/Spansion/Cypress/Infineon, and now Marvell, Susan has worked on various IC products including microprocessor, networking, Flash memory, MCU, Type-C USB, wireless IoT, and now AI Chiplet devices. Her main focus is to support design teams, product lines and manufacturing groups for debugging new products, analyzing customer returns, and performing failure analysis on existing products for quality, reliability and yield improvement.
Before joining AMD, Susan earned a Master of Engineering degree in Materials Science and Engineering from Carnegie Mellon University, Pittsburgh, Pennsylvania, and a Bachelor of Engineering degree in Electronics Engineering from Peking University, China. She has published more than 30 papers at international conferences and currently holds 21 US patents.
Susan has been working with ISTFA Organizing Committee in the past 20 years and IPFA Technical Program Steering Committee in the past 15 years. She served two terms as a board member for Electronic Device Failure Analysis Society (EDFAS) and was the General Chair for International Symposium for Testing and Failure Analysis (ISTFA) in 2021.
The adoption of Chip Scale Packages (CSPs) has been one of the most significant and successful trends in the electronics industry since their introduction in the early 90s. CSPs are well accepted by the electronic industry due to their many benefits. They have the advantage of smaller size and low package profile, lesser weight, relatively easier assembly process, lower overall manufacturing costs and improved electrical performance. With their reduced package size compared to traditional leaded packages, CSPs are ideal for the applications of cell phones, smart devices, laptops and digital cameras that require better use of real estate on the PC boards. Recent developments of System in Package (SiP) have pushed the CSP applications to the highest level for miniaturization of the entire system.
However, the reduced package size of CSPs has created challenges for this type of package during failure analysis process. In this tutorial, an overview of CSPs and their applications will be provided, and some challenges in performing failure analysis on CSPs will be revealed, particularly for CSPs in special package configurations such as stacked die Multi-Chip-Packages (MCP), Wafer Level CSPs, and 2.5D and 3D SiPs. Some special failure analysis tools and techniques will be discussed for effectively analyzing the CSPs. Finally, solutions and best practices will be shared on how to overcome these challenges. Several case studies will be presented at the end of tutorial to demonstrate how failure analysis work can be successfully completed on CSP devices.
Semitracks, Inc. President
Christopher Henderson received his B.S. in Physics from the New Mexico Institute of Mining and Technology and his M.S.E.E. from the University of New Mexico. Chris is the President and one of the founders of Semitracks, Inc., a United States-based company that provides education and semiconductor training to the electronics industry.
From 1988 to 2004, Chris worked at Sandia National Laboratories, where he was a Principal Member of Technical Staff in the Failure Analysis Department and Microsystems Partnerships Department. His job responsibilities have included manufacturing, testing, reliability and yield analysis of components fabricated at Sandia’s Microelectronics Development Laboratory, research into the electrical behavior of defects, and consulting on microelectronics issues for the DoD.
He has published over 25 papers at various conferences in semiconductor processing, reliability, failure analysis, and test. He has received two R&D 100 awards and two best paper awards. Prior to working at Sandia, Chris worked for Honeywell, BF Goodrich Aerospace, and Intel. Chris is a Senior Member of IEEE and EDFAS (the Electron Device Failure Analysis Society). He was the General Chair of the International Symposium for Testing and Failure Analysis (ISTFA) in 2007 and the General Chair of the IEEE Reliability Physics Symposium in 2016.
At Semitracks, Inc., Chris teaches courses on semiconductor processing, failure and yield analysis, semiconductor reliability, and other aspects of semiconductor technology. His team has developed an extensive Online Training platform for self-paced learning, as well as AI-based learning guidance, and virtual reality training for equipment operation and maintenance.
Leading edge foundries are finishing the development of the next generation technology that will replace the existing FinFET technology architecture. This next generation technology stacks the P- and N-channel transistors vertically, and is sometimes referred to as a Complementary Field Effect Transistor, or CFET technology. Furthermore, routing power to these transistors requires providing power from not only the frontside of the chip, but also from the backside of the chip. Companies designing leading edge products that will use this technology will need to be able to test these products to ensure they will work properly in their customers’ applications. Traditionally, test engineers have used defect-based based testing approaches to identify problems with circuits that do not work correctly. This includes current-based test techniques, delay-based techniques, and other methods. These techniques can also provide the basis for the electrical stimulus needed to perform failure analysis on these circuits. An important question to consider is whether or not these traditional techniques can work on CFET technologies. In this tutorial, we will explore some of the issues surrounding defect-based testing of these leading-edge circuits, how test engineers plan to test them, and whether or not failure analysis engineers can take advantage of these test techniques to aid in the analysis of these chips.
Senior Application Engineer, JEOL Asia Pte Ltd
Dr. Jen-It Wong currently hold the position of Senior Application Engineer at JEOL Asia Pte Ltd. He obtained both Beng (Hons) and PhD degrees from Nanyang Technological University (NTU), Singapore. He specialized in utilizing aberration corrected scanning & transmission electron microscope (STEM) to meet client’s R&D objectives. In additions, he also helped maximize client’s investment through efficient usage and in-depth understanding of STEM system via training, education. He supported Prof Steve Pennycook research group during his time at the National University of Singapore (NUS).
He has served as reviewer for IEEE Transactions on Electron Devices (T-ED), Nanoscience & Nanotechnology Letters (NNL), Journal of Luminescence as well as Materials & Design. His current research interests are in the area of functional nanomaterials with particular focus to their application in optoelectronic devices, bio & toxic gas sensing.
For more information, please visit https://www.jenit.net
Jen-It Wong1*, Rizuan Mohd Rosnan2 and Tetsuo Oikawa1
Transmission Electron Microscope (TEM) and Scanning TEM (STEM) are indispensable in modern semiconductor characterization. Recent progress in the aberration-corrected STEM and the commercialization of cold field emission gun (CFEG) [1,2,3] has fueled the utilization of such tools in once unchartered regime of atom to atom observations with localized details [4]. TEM & STEM has been used routinely for metrological and failure analysis purposes, but thorough understanding of this tool and related techniques is less known to the wider community due to the complexity of the tool.
In this tutorial, we will be reviewing current aberration corrector technologies from electron optics perspective and their implications for technological advancement. Moreover, we will also be briefly reviewing those related TEM & STEM techniques that have been used routinely, for example, Energy-dispersive X-ray spectroscopy (EDS) [5], Electron Energy Loss Spectroscopy (EELS) [6] as well as some other techniques that can be useful for failure analysis. We will also be introducing some emerging techniques [7] and their possible application to semiconductor characterization. In a nutshell, you should expect to understand how all these TEM & STEM techniques work by the end of this tutorial.
References:
Acknowledgement:
The authors acknowledge support from team members of JEOL Ltd., Application Department
Assoc Prof of Universiti Sains Malaysia
Dr Fei-Yee YEOH is an Associate Professor at the School of Materials & Mineral Resources Engineering, Universiti Sains Malaysia (USM) since 2008. He was also the former Director of Industry Network for the university from 2016 to 2021. Fei Yee completed his master study with the best thesis award in Materials Engineering, USM in 2004 under a special scholarship scheme. He was awarded with AUN/Seed-Net Scholarship by Japan International Cooperation Agency (JICA) for his doctoral research in Functional Materials Engineering at Toyohashi University of Technology, Japan. Fei has been appointed by many companies and government agencies as a technical and strategy consultant to provide consultancy and training in topics such as materials engineering and characterization, blue ocean strategy, industry 4.0 and ESG. His current research focuses on conversion of nanoporous materials from wastes and biomasses into sustainable value-added materials for clean energy, water security and environmental applications.
Prior to his academic career as a faculty member, he was also an R&D engineer specialized on materials in a multinational company. Between 2015-2016, he was appointed by the Ministry of Higher Education (MOHE) to carry out postdoctoral research on nanomaterials in IBM, Silicon Valley. As a researcher, Dr Yeoh had completed more than >50 research projects including 20> international grants, with a total value of more than RM10 million, producing >50 papers, books and chapters and several intellectual properties mostly as a corresponding author in Q1/Q2 ISI journal. He was also a strategy planning consultant for the Ministry of Higher Education, and a technology consultant to several companies.
The growing field of nanotechnology has opened up new avenues for the development of advanced semiconductor devices with enhanced performance and functionality. This paper focuses on the various characterization techniques of nano-materials and biocompatible materials for potential applications in semiconductor technology. Through a combination of a wide range of material characterization techniques, such as scanning electron microscopy (SEM), transmission electron microscopy (TEM), X-ray diffraction (XRD), atomic force microscopy (AFM) and adsorption techniques, the structural, morphological, physical and chemical properties of these materials could be investigated. Meanwhile, biocompatibility assessments such as cytotoxicity and hemocompatibility could be conducted to evaluate their suitability for biomedical applications. However, during the characterization process, numerous challenges were encountered such as, stability and handling of nano-materials during phase transition or condition changes, imaging resolution of the materials and cell morphology interacting with biocompatible materials. The evolving industry 4.0 technology may offer a potential solution with the incorporation of various technology enablers such as IOT, big data, advanced analytics, artificial intelligence and 3D printing into the present or emerging characterization techniques to further advance the study.
Institute of Microengineering and Nanoelectronics Universiti Kebangsaan Malaysia
Azman Jalar (Ph.D, Birmingham University, UK, 2001) is a professor of applied metallurgy from Department of Applied Physics, Universiti Kebangsaan Malaysia (UKM). He is also a Principal Research Fellow of Institute of Microengineering and Nanoelectronics (IMEN) and theme leader of Microelectronics Packaging (MiPAC) and Group Leader of UKM Research Group ‘Electronics Components Materials and Packaging’. His career started in the field of physical and mechanical metallurgy focused in alloy development since 1990s. His involvement in electronics packaging started in 2002 when he was approached by engineer from OnSemi to solve thermally activated process in wire bonding. Since then, his interest on structure-properties-performance relationship motivates him to works in many areas of semiconductor packaging research and development including materials, packaging architecture, failure analysis, assembly and test. Strong background in materials science and metallurgy enable him to help in solving many industrial issues in semiconductor industry. He is referred by several industrial players such as OnSemi, Freescale, Texas Instruments, Nexperia, Western Digital, Jabil electronics, Celestica, AIC electronics, Infineon, Carsem, Stats ChipPac, and many manufacturing services company such as solder manufactures, plating, smelting, moulding compound and many more. He trained more than 70 postgraduate students by research which half of them associate with electronics industry, develop modules, courses and conduct training related to semiconductor manufacturing industry for higher degree, professional development and knowledge advancement.
Failure analysis in semiconductor manufacturing and assembly is a systematic process used to identify the root cause of defects or failures in semiconductor devices. This analysis is crucial because even minor defects in semiconductor components can significantly affect the performance, reliability, and yield of electronic devices. By understanding the failure mechanisms, manufacturers can implement corrective actions, improve process control, enhance product reliability, and reduce costs associated with faulty components.
The ‘materials science paradigm’ is a conceptual framework that describes the relationship between the fundamental aspects of materials – structure, properties, processing, and performance. These four components form a loop or cycle, often referred to as the “materials science tetrahedron” because they are interdependent and influence each other. On top of these, the ‘cost’ also is included as economic driven activities. Understanding this relationship is crucial for materials design and engineering, as it allows scientists and engineers to tailor materials to meet specific functional requirements.
The ‘characterisation’ is the means to describe the relationship between structure-properties-performance-processing. Due to materials science paradigm shift, the ‘characterisation’ evolves from empirical, model based theoretical science, computational science and data-driven science. Typical characterisation activities involve engineering/characterisation tools (such as microscopy, elemental and chemical analysis, FMEA, RCA), design and simulation tools including software, quality engineering tools (e.g. SPC, DMIAC) and many more. Latest developments in machine learning and artificial intelligence have shifted this typical characterisation by integrating the ML and AI in describing the structure-properties-performance-processing relationship.
This tutorial will discuss the nature of structure-properties-processing-performance relationship by describing major factors of structure as the building block of the devices – how this structure from viewpoint of atomic arrangement, leading to various respond towards its properties and performance, either for same ‘material/element’ or combination of them. The ‘characterisation’ activities will also be discussed based on real failure analysis via conventional and data-driven/ML/AI integrated analysis.
Professor Emeritus
Department of Electrical and Computer Engineering,
National University of Singapore
Prof. Chua Soo-Jin graduated with a B.Eng (1st class Hons) from the University of Singapore in 1974 and his PhD from the University of Wales, United Kingdom in 1977. In 1978, he worked for Standard Telecommunications Labs, Harlow, UK, as a research scientist. In 1981, he spent a year at the Fraunhofer Institute of Semiconductor Technology, Munich under a German Exchange Scholarship (DAAD). He was a Visiting Fellow of Japan Society for the Promotion of Science in 1988 and of the British Council in 1990. While serving as an academic staff at NUS since 1979, he concurrently held positions in the research institutes in Singapore. He was Principal Scientist in the Institute of Materials Research and Engineering (IMRE) 1999 – 2010, and Principal Investigator in Singapore-MIT Alliance for Research and Teaching (SMART) 2012 – 2017. He was Deputy Director of the Singapore-MIT Alliance (SMA) from 1999 – 2014, Executive Deputy Director, IMRE from 2004- 2010, Assistant Director of the Institute of Microelectronics from 1991- 1995 and Director of the Centre for Optoelectronics, Department of Electrical and Computer Engineering, NUS from 1990 – 2010. Currently, he is Professor Emeritus in the Department of Electrical Engineering, National University of Singapore.
Prof Chua has over 700 publications, h-index of 69 and a citation exceeding 20,000. His research area is in III-Nitrides grown by MOCVD, ZnO by hydrothermal synthesis, fabrication of optoelectronic devices such as semiconductor lasers and optical waveguide components and applications of nanostructures, photonic bandgap crystals and plasmonics in Optoelectronics. He was editor of J Phys D Semiconductor Photonic Materials and Devices 2020 – 2022. He is still active in giving lectures and courses in his field of expertise at NUS, in industry and at various universities in China.
Reliability of LEDs is impacted by several factors. They can be categorized in the following ways
The failure of a device can be gradual or catastrophic. Gradual failure is seen in the gradual reduction in intensity over time due to the accumulation of defects in the active layer. Several device designs are discussed in relation to how the device characteristics change with time and temperature. Catastrophic failure is seen as the sudden or abrupt cessation of light output and may be due to electrostatic discharge puncturing the pn junction (short-cuit) or the delamination on the lead contacts (open-circuit).
Topics to be discussed include the following:
Dean of School of Integrated Circuits, Tsinghua University
Prof. Huaqiang Wu is currently the Dean of School of Integrated Circuits, Tsinghua University, Beijing, China. He received the bachelor degree in MSE from Tsinghua University in 2000. In 2005, he received Ph.D. in EE from Cornell University. After that, he worked for AMD and Spansion as Senior Research Engineer, working on advanced Flash memory devices. He joined Tsinghua University in 2009 as associate professor, and became full professor in 2018.
His research topics include the emerging memory devices and alternative computing paradigms. He has authored more than 200 journal papers and conference proceedings on Science, Nature, Nature Nanotechnology, Nature Electronics, ISSCC, IEDM, VLSI, etc. He holds over 100 patents in the US and China, with more than 30 commercialized, and has incubated four high-tech companies, successfully bringing resistive memory technology to market.
He serves as an associate editor of IEEE EDL and TCAS-II, the TPC chair of EDTM 2021, and TPC member of VLSI and VLSI-TSA. He has given multiple invited talks at IEDM, IRPS, IMW, MRS, GLS-VLSI, etc. He received the inaugural Xplorer prize and the National Science Fund for Distinguished Young Scholars from NSFC.
This tutorial will bridge the evolution of Computing-In-Memory (CIM) technologies and the unique reliability challenges posed by metal oxide based Resistive Random Access Memory (RRAM). It starts with the foundational aspects of CIM technology, advancements in memristor, and their revolutionary role in the semiconductor industry and artificial intelligence. The reliability requirements of RRAM in both conventional digital memory applications and the neuromorphic computing are compared, highlighting the importance of retention and endurance as critical device metrics. Through statistical measurements and system simulations, we will reveal the distinct degradation behaviors of oxide-based RRAM when integrated into neuromorphic systems. Furthermore, the tutorial will introduce the various methods employed to characterize reliability concerns within memristor-based CIM for reliability assessment, as well as the most effective optimization strategies aimed at risk reduction and performance enhancement. In the end, we will introduce a full-system-integrated chip to support complete on-chip learning, aiming for various edge intelligence applications. The end-to-end on-chip improvement learning is demonstrated across various tasks, including motion control, image classification, and speech recognition, achieving software-comparable accuracy and low hardware cost
After obtaining his PhD from London University, Alastair worked in Microelectronics R&D for over three decades, at GEC Marconi Research in the UK and at the Institute of Microelectronics (IME) in Singapore. He has worked extensively in materials characterisation, failure analysis, microelectronics packaging, reliability and surface analysis. In 2018, he was reliability consultant at Denselight Semiconductors in Singapore focused on Telcordia qualification for photonic devices. He has delivered training seminars in the fields of surface analysis, microelectronics failure analysis, microelectronics reliability, RF Package Technology, and project management for R&D.
He is a Life Member of IEEE and was active in organising IPFA conferences for several years, being general chair of the 12th & 13th IPFA conferences held in Singapore in 2005 & 2006.
The tutorial will focus on the most important surface analysis techniques used in the microelectronics industry. The introduction will explain first why surfaces are so important; they are where materials interact with the environment and with each other. It will also consider what we mean by “surface” and, briefly, why an ultra-high vacuum is usually essential for analysis. The following techniques will be described along with their strengths, applications and weaknesses: Auger Electron Spectroscopy (AES), X-Ray Photoelectron Spectroscopy (XPS), Total Reflection X-ray Fluorescence (TXRF) and Secondary Ion Mass Spectrometry (SIMS), the last of which comes in two “flavours”: Time of Flight Secondary Ion Mass Spectrometry (TOF-SIMS) and Dynamic SIMS. Finally, there will be a discussion of scanning probe microscopy focussed on the most widely used mode, Atomic Force Microscopy (AFM). In the conclusion, a strategy for deciding on the most appropriate analysis strategy will be presented.